Commit 30e31a95 authored by Ján Labuda's avatar Ján Labuda
Browse files

Merge branch 'main' of https://gitlab.fi.muni.cz/xlabuda2/fpga-uart

marge
parents c7b73f22 3f0a38d9
module receiver_example(
input wire _CLOCK_50,
input wire _KEY,
inout wire _GPIO_0,
output reg [7:0] _LEDR
);
wire RX;
assign RX = _GPIO_0;
wire uart_clock;
wire[7:0] uart_data;
clock_divider divider(
.clock(_CLOCK_50),
.out(uart_clock)
);
defparam divider.divider = 62; /* 115.2 * 7 kHz */
//defparam divider.divider = 50_000_000;
receiver receiver(
.in(RX),
//.in(_KEY),
.clock(uart_clock),
.out(uart_data)
);
always @(posedge _CLOCK_50)
begin
_LEDR <= uart_data;
end
endmodule
module transmiter_example(
input _CLOCK_50,
input _KEY,
input [7:0] _SW,
inout _GPIO_0
);
reg TX;
wire[9:0] SWITCH;
assign SWITCH = _SW;
assign _GPIO_0 = TX;
reg[7:0] uart_data;
reg uart_start;
wire uart_clock;
wire uart_bit;
clock_divider divider(
.clock(_CLOCK_50),
.out(uart_clock)
);
defparam divider.divider = 434; /* 115.2 kHz */
transmiter trensmit(
.clock(uart_clock),
.start(uart_start),
.data(uart_data),
.out(uart_bit)
);
always @(posedge _CLOCK_50)
begin
uart_data <= SWITCH[7:0];
uart_start <= !_KEY;
TX <= uart_bit;
end
endmodule
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment