Commit 3f0a38d9 authored by Ján Labuda's avatar Ján Labuda
Browse files

Delete transmiter_example.v

parent d700c8f4
module transmiter_example(
input _CLOCK_50,
input _KEY,
input [7:0] _SW,
inout _GPIO_0
reg TX;
wire[9:0] SWITCH;
assign SWITCH = _SW;
assign _GPIO_0 = TX;
reg[7:0] uart_data;
reg uart_start;
wire uart_clock;
wire uart_bit;
clock_divider divider(
defparam divider.divider = 434; /* 115.2 kHz */
transmiter trensmit(
always @(posedge _CLOCK_50)
uart_data <= SWITCH[7:0];
uart_start <= !_KEY;
TX <= uart_bit;
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