Commit d700c8f4 authored by Ján Labuda's avatar Ján Labuda
Browse files

Delete receiver_example.v

parent 73d74827
module receiver_example(
input wire _CLOCK_50,
input wire _KEY,
inout wire _GPIO_0,
output reg [7:0] _LEDR
);
wire RX;
assign RX = _GPIO_0;
wire uart_clock;
wire[7:0] uart_data;
clock_divider divider(
.clock(_CLOCK_50),
.out(uart_clock)
);
defparam divider.divider = 62; /* 115.2 * 7 kHz */
//defparam divider.divider = 50_000_000;
receiver receiver(
.in(RX),
//.in(_KEY),
.clock(uart_clock),
.out(uart_data)
);
always @(posedge _CLOCK_50)
begin
_LEDR <= uart_data;
end
endmodule
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