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Commit c7b73f22 authored by Ján Labuda's avatar Ján Labuda
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feat: init state for frequency

parent 73d74827
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display.v 0 → 100644
View file @ c7b73f22
module display(
input wire[23:0] data,
output wire[41:0] digits
);
segment digit0(
.data(data[3:0]),
.segment_value(digits[6:0])
);
segment digit1(
.data(data[7:4]),
.segment_value(digits[13:7])
);
segment digit2(
.data(data[11:8]),
.segment_value(digits[20:14])
);
segment digit3(
.data(data[15:12]),
.segment_value(digits[27:21])
);
segment digit4(
.data(data[19:16]),
.segment_value(digits[34:28])
);
segment digit5(
.data(data[23:20]),
.segment_value(digits[41:35])
);
endmodule
prescaler_state_machine.v 0 → 100644
View file @ c7b73f22
/**
*
* @param
* @param
* @param
* @param
* @param
*/
module prescaler_state_machine(
input wire clock,
input wire reset,
input wire next,
output reg[3:0] prescale_value,
output reg[23:0] prescale_display
);
reg[3:0] state;
localparam state_9600 = 4'd0;
localparam state_9600_press = 4'd1;
localparam state_19200 = 4'd2;
localparam state_19200_press = 4'd3;
localparam state_38400 = 4'd4;
localparam state_38400_press = 4'd5;
localparam state_57600 = 4'd6;
localparam state_57600_press = 4'd7;
localparam state_115200 = 4'd8;
localparam state_115200_press = 4'd9;
/* State machine. */
always @(posedge clock)
begin
if (reset)
begin
state <= state_9600;
end
else
begin
case (state)
state_9600 : state <= (next) ? state_9600_press : state_9600;
state_9600_press : state <= (!next) ? state_19200 : state_9600_press;
state_19200 : state <= (next) ? state_19200_press : state_19200;
state_19200_press : state <= (!next) ? state_38400 : state_19200_press;
state_38400 : state <= (next) ? state_38400_press : state_38400;
state_38400_press : state <= (!next) ? state_57600 : state_38400_press;
state_57600 : state <= (next) ? state_57600_press : state_57600;
state_57600_press : state <= (!next) ? state_115200 : state_57600_press;
state_115200 : state <= (next) ? state_115200_press : state_115200;
state_115200_press : state <= (!next) ? state_9600 : state_115200_press;
endcase
end
end
/* Set prescaler value. */
always @(posedge clock)
begin
case (state)
state_9600 : prescale_value <= 4'd12;
state_9600_press : prescale_value <= 4'd12;
state_19200 : prescale_value <= 4'd6;
state_19200_press : prescale_value <= 4'd6;
state_38400 : prescale_value <= 4'd3;
state_38400_press : prescale_value <= 4'd3;
state_57600 : prescale_value <= 4'd2;
state_57600_press : prescale_value <= 4'd2;
state_115200 : prescale_value <= 4'd1;
state_115200_press : prescale_value <= 4'd1;
endcase
end
/* Set display value. */
always @(posedge clock)
begin
case (state)
state_9600 : prescale_display <= 24'h9600;
state_9600_press : prescale_display <= 24'h9600;
state_19200 : prescale_display <= 24'h19200;
state_19200_press : prescale_display <= 24'h19200;
state_38400 : prescale_display <= 24'h38400;
state_38400_press : prescale_display <= 24'h38400;
state_57600 : prescale_display <= 24'h57600;
state_57600_press : prescale_display <= 24'h57600;
state_115200 : prescale_display <= 24'h115200;
state_115200_press : prescale_display <= 24'h115200;
endcase
end
endmodule
segment.v 0 → 100644
View file @ c7b73f22
module segment(
input wire[3:0] data,
output reg[6:0] segment_value
);
always @(data)
begin
case (data)
4'h0 : segment_value = 7'b1000000;
4'h1 : segment_value = 7'b1111001;
4'h2 : segment_value = 7'b0100100;
4'h3 : segment_value = 7'b0110000;
4'h4 : segment_value = 7'b0011001;
4'h5 : segment_value = 7'b0010010;
4'h6 : segment_value = 7'b0000010;
4'h7 : segment_value = 7'b1111000;
4'h8 : segment_value = 7'b0000000;
4'h9 : segment_value = 7'b0011000;
4'hA : segment_value = 7'b0001000;
4'hb : segment_value = 7'b0000011;
4'hC : segment_value = 7'b1000110;
4'hd : segment_value = 7'b0100001;
4'hE : segment_value = 7'b0000110;
4'hF : segment_value = 7'b0001110;
default: segment_value = 7'b1111111;
endcase
end
endmodule
uart.qsf
View file @ c7b73f22
......@@ -205,4 +205,7 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE clock_divider.v
set_global_assignment -name VERILOG_FILE transmiter.v
set_global_assignment -name VERILOG_FILE receiver.v
set_global_assignment -name VERILOG_FILE prescaler_state_machine.v
set_global_assignment -name VERILOG_FILE display.v
set_global_assignment -name VERILOG_FILE segment.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
uart.qws
View file @ c7b73f22
No preview for this file type
uart.v
View file @ c7b73f22
......@@ -3,11 +3,18 @@
* wait for two bytes and send back the bigger one.
*/
module uart(
input CLOCK_50,
input [3:0] KEY,
input [9:0] SW,
inout [1:0] GPIO_0,
output [9:0] LEDR
input CLOCK_50,
input wire[3:0] KEY,
input wire[9:0] SW,
inout wire[1:0] GPIO_0,
output wire[9:0] LEDR,
output wire[6:0] HEX0,
output wire[6:0] HEX1,
output wire[6:0] HEX2,
output wire[6:0] HEX3,
output wire[6:0] HEX4,
output wire[6:0] HEX5
);
wire TX;
......@@ -21,7 +28,7 @@ module uart(
wire uart_transmitter_clock;
wire uart_receiver_clock;
clock_divider _uart_transmitter_clock(
/*clock_divider _uart_transmitter_clock(
.clock(CLOCK_50),
.out(uart_transmitter_clock)
);
......@@ -32,7 +39,7 @@ module uart(
);
defparam _uart_transmitter_clock.divider = 434;
defparam _uart_receiver_clock.divider = 62;
defparam _uart_receiver_clock.divider = 62;*/
/* Predefine UART registers and wires. */
reg[7:0] uart_transmit_data;
......@@ -44,7 +51,7 @@ module uart(
wire uart_receiver_ready;
/* Set UART modules. */
transmiter _trensmiter(
/* transmiter _trensmiter(
.clock(uart_transmitter_clock),
.start(uart_transmit_start),
.data(uart_transmit_data),
......@@ -58,7 +65,7 @@ module uart(
.clear_flag(uart_receiver_clear),
.out(uart_receiver_data),
.ready(uart_receiver_ready)
);
);*/
/* Define state machine. */
reg[2:0] state;
......@@ -84,7 +91,7 @@ module uart(
localparam second_delay = 115200;
/* Main loop */
always @(posedge uart_transmitter_clock)
/* always @(posedge uart_transmitter_clock)
begin
LED <= state;
......@@ -141,6 +148,40 @@ module uart(
end
end
endcase
end*/
wire clk;
clock_divider simple_divider(
.clock(CLOCK_50),
.out(clk)
);
defparam simple_divider.divider = 434;
wire[3:0] prescale_value_pick;
wire[23:0] prescale_display_pick;
reg [23:0] baudrate;
reg [3:0] prescale_value;
display display(
.data(baudrate),
.digits({HEX5, HEX4, HEX3, HEX2, HEX1, HEX0})
);
prescaler_state_machine prescale_module(
.clock(CLOCK_50),
.reset(!KEY[0]),
.next(!KEY[1]),
.prescale_value(prescale_value_pick),
.prescale_display(prescale_display)
);
always @(posedge CLOCK_50)
begin
LED <= prescale_value_pick;
baudrate <= prescale_display_pick;
end
endmodule
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