feat: UART bit transmission

clock_divider.v

 module clock_divider(
-	input wire clock,
-	input wire reset,
-	
-	output reg out
+    input wire clock,
+    input wire reset,
+    
+    output reg out
 );
-	
-	parameter divider = 32'd50_000_000;
+    
+    parameter divider = 32'd50_000_000;
 
-	reg [31:0] 	counter;
+    reg [31:0]  counter;
 
-	always @(posedge clock)
-	begin
-		if (reset || !counter)
-			counter <= divider;
-		else
-			counter <= counter - 1;
-		
-		out <= counter == 0;
-	end
+    always @(posedge clock)
+    begin
+        if (reset || !counter)
+            counter <= divider;
+        else
+            counter <= counter - 1;
+        
+        out <= counter == 0;
+    end
 
 endmodule

transmiter.v

 module transmiter(
-	input wire 			clock,
-	input wire 			start,
-	input wire[7:0]	data,
-	
-	output reg ready 			,//TODO REMOVE
-	output reg out
+    input wire      clock,
+    input wire      start,
+    input wire[7:0] data,
+    
+    output reg ready            ,//TODO REMOVE
+    output reg out
 );
+    
+    parameter start_bit = 1;
+    parameter stop_bit  = 1;
 
-	reg [7:0] _data;
-	reg [3:0] _to_transmit;
-	
-	always @(posedge clock, posedge start)
-	begin
-		if (start)
-		begin
-			ready	<= 0;
-			
-			_to_transmit 	<= 8;
-			_data 			<= data;
-		end
-		else if (_to_transmit > 0)
-		begin
-			out <= _data[7];
-			
-			_to_transmit 	<= _to_transmit - 1;
-			_data 			<= _data << 1;
-		end
-		else
-		begin
-			out 		<= 0;
-			ready 	<= 1;
-		end
-	end	
-	
+    reg [9:0] _data;
+    reg [3:0] _to_transmit;
+    
+    always @(posedge clock, posedge start)
+    begin
+        if (start)
+        begin
+            if (ready)
+            begin
+                out     <= 0;
+                ready   <= 0;
+                
+                _to_transmit    <= 10;
+                _data           <= (start_bit << 9) | (data << 1) | stop_bit; 
+            end
+        end
+        else if (_to_transmit > 0)
+        begin
+            out <= _data[9];
+            
+            _to_transmit    <= _to_transmit - 1;
+            _data           <= _data << 1;
+        end
+        else
+        begin
+            out     <= 0;
+            ready   <= 1;
+        end
+    end 
+    
 endmodule

uart.v

 module uart(
-	input 			CLOCK_50,
-	input		[3:0] KEY,
-	input 	[9:0]	SW,
-	output	[9:0]	LEDR
+    input           CLOCK_50,
+    input   [3:0]   KEY,
+    input   [9:0]   SW,
+    output  [9:0]   LEDR
 );
 
-	reg[9:0] LED;
-	reg[7:0] my_data;
-	reg my_start;
-	wire[9:0] SWITCH;
-	wire my_clock;
-	wire my_ready;
-	wire my_received;
-	
-	clock_divider div(
-		.clock(CLOCK_50),
-		.reset(!KEY[0]),
-		.out(my_clock)
-	);
-	
-	transmiter trensmit(
-		.clock(my_clock),
-		.start(my_start),
-		.data(my_data),
-		.ready(my_ready),
-		.out(my_received)
-	);
-	
-	defparam div.divider = 12_500_000;
-	
-	assign LEDR = LED;
-	assign SWITCH = SW;
+    reg[9:0] LED;
+    reg[7:0] my_data;
+    wire[9:0] SWITCH;
+    wire my_clock;
+    wire my_ready;
+    wire my_received;
+    
+    clock_divider div(
+        .clock(CLOCK_50),
+        .reset(!KEY[0]),
+        .out(my_clock)
+    );
+    
+    transmiter trensmit(
+        .clock(my_clock),
+        .start(!KEY[1]),
+        .data(my_data),
+        .ready(my_ready),
+        .out(my_received)
+    );
+    
+    defparam div.divider = 12_500_000;
+    
+    assign LEDR = LED;
+    assign SWITCH = SW;
 
-	always @(posedge CLOCK_50)
-	begin
-		my_data = SWITCH[7:0];
-		
-		my_start <= my_ready;
-			
-		LED = my_received;
-	end
+    always @(posedge CLOCK_50)
+    begin
+        my_data <= SWITCH[7:0];            
+        LED <= my_received;
+    end
 
 endmodule