feat: add serial transmission

clock_divider.v

-module clock_divider(clock, reset, out);
-	input clock, reset;
-	parameter divider = 32'd50_000_000;
-	output out;
+module clock_divider(
+	input wire clock,
+	input wire reset,
+	
+	output reg out
+);
 	
-	reg [31:0] counter;
-	reg out;
+	parameter divider = 32'd50_000_000;
+
+	reg [31:0] 	counter;
 
 	always @(posedge clock)
 	begin

transmiter.v

+module transmiter(
+	input wire 			clock,
+	input wire 			start,
+	input wire[7:0]	data,
+	
+	output reg ready 			,//TODO REMOVE
+	output reg out
+);
+
+	reg [7:0] _data;
+	reg [3:0] _to_transmit;
+	
+	always @(posedge clock, posedge start)
+	begin
+		if (start)
+		begin
+			ready	<= 0;
+			
+			_to_transmit 	<= 8;
+			_data 			<= data;
+		end
+		else if (_to_transmit > 0)
+		begin
+			out <= _data[7];
+			
+			_to_transmit 	<= _to_transmit - 1;
+			_data 			<= _data << 1;
+		end
+		else
+		begin
+			out 		<= 0;
+			ready 	<= 1;
+		end
+	end	
+	
+endmodule

uart.qsf

@@ -203,4 +203,5 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VERILOG_FILE clock_divider.v
+set_global_assignment -name VERILOG_FILE transmiter.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

uart.v

 module uart(
-	input 		          		CLOCK_50,
-	output		     [9:0]		LEDR,
-	input					[3:0] 	KEY,
-	input 		     [9:0]		SW
+	input 			CLOCK_50,
+	input		[3:0] KEY,
+	input 	[9:0]	SW,
+	output	[9:0]	LEDR
 );
 
-	reg [9:0] LED;
-	wire [9:0] SWITCH;
+	reg[9:0] LED;
+	reg[7:0] my_data;
+	reg my_start;
+	wire[9:0] SWITCH;
 	wire my_clock;
+	wire my_ready;
+	wire my_received;
 	
-	clock_divider five_seconds(
+	clock_divider div(
 		.clock(CLOCK_50),
 		.reset(!KEY[0]),
 		.out(my_clock)
 	);
 	
-	defparam five_seconds.divider = 250_000_000;
+	transmiter trensmit(
+		.clock(my_clock),
+		.start(my_start),
+		.data(my_data),
+		.ready(my_ready),
+		.out(my_received)
+	);
+	
+	defparam div.divider = 12_500_000;
 	
 	assign LEDR = LED;
 	assign SWITCH = SW;
 
 	always @(posedge CLOCK_50)
 	begin
-		if (my_clock)
-			LED <= ~LED;
+		my_data = SWITCH[7:0];
+		
+		my_start <= my_ready;
+			
+		LED = my_received;
 	end
 
 endmodule