feat: add clock

clock_divider.v

+module clock_divider(clock, reset, out);
+	input clock, reset;
+	parameter divider = 32'd50_000_000;
+	output out;
+	
+	reg [31:0] counter;
+	reg out;
+
+	always @(posedge clock)
+	begin
+		if (reset || !counter)
+			counter <= divider;
+		else
+			counter <= counter - 1;
+		
+		out <= counter == 0;
+	end
+
+endmodule

uart.qsf

@@ -202,4 +202,5 @@ set_global_assignment -name VERILOG_FILE uart.v
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE clock_divider.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

uart.v

 module uart(
 	input 		          		CLOCK_50,
 	output		     [9:0]		LEDR,
+	input					[3:0] 	KEY,
 	input 		     [9:0]		SW
 );
 
 	reg [9:0] LED;
 	wire [9:0] SWITCH;
+	wire my_clock;
+	
+	clock_divider five_seconds(
+		.clock(CLOCK_50),
+		.reset(!KEY[0]),
+		.out(my_clock)
+	);
+	
+	defparam five_seconds.divider = 250_000_000;
 	
 	assign LEDR = LED;
 	assign SWITCH = SW;
 
-always @(posedge CLOCK_50)
-begin
-	LED <= SWITCH;
-end
+	always @(posedge CLOCK_50)
+	begin
+		if (my_clock)
+			LED <= ~LED;
+	end
 
 endmodule