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Ján Labuda
FPGA - UART
Commits
0a706608
Commit
0a706608
authored
Dec 13, 2021
by
Ján Labuda
Browse files
feat: submission
parent
f35fac27
Changes
2
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uart.py
View file @
0a706608
...
...
@@ -30,4 +30,5 @@ if __name__ == '__main__':
y
=
int
(
input
(
'Second number: '
))
send
(
'COM3'
,
y
)
print
(
'output: '
,
readBlock
(
'COM3'
))
print
(
'output: '
,
int
.
from_bytes
(
readBlock
(
'COM3'
),
byteorder
=
'little'
))
uart.v
View file @
0a706608
...
...
@@ -78,14 +78,15 @@ module uart(
assign
LEDR
=
LED
;
/* So USB can read data. */
reg
[
31
:
0
]
delay
;
/*remove*/
reg
prev
;
localparam
second_delay
=
115200
;
/* Main loop */
always
@
(
posedge
uart_transmitter_clock
)
begin
LED
<=
first_byte
|
second_by
te
;
begin
LED
<=
sta
te
;
case
(
state
)
state_wait_for_first:
...
...
@@ -115,16 +116,25 @@ module uart(
begin
state
<=
state_send_data
;
uart_receiver_clear
<=
0
;
delay
<=
second_delay
;
end
state_send_data:
begin
state
<=
state_data_sent
;
uart_transmit_data
<=
(
first_byte
>
second_byte
)
?
first_byte
:
second_byte
;
uart_transmit_start
<=
1
;
if
(
delay
>
0
)
begin
delay
<=
delay
-
1
;
end
if
(
delay
==
0
&&
uart_transmit_ready
==
1
)
begin
state
<=
state_data_sent
;
uart_transmit_data
<=
(
first_byte
>
second_byte
)
?
first_byte
:
second_byte
;
uart_transmit_start
<=
1
;
end
end
state_data_sent:
begin
if
(
uart_transmit_ready
)
if
(
uart_transmit_ready
==
0
)
begin
state
<=
state_wait_for_first
;
uart_transmit_start
<=
0
;
...
...
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