feat: init example

receiver.v

@@ -3,7 +3,7 @@
  *
  * @param in            - UART link wire
  * @param clock         - clock with 7 times higher frequency then UART
- * @param clear_flag    - on rising edge, ready flag will be cleared
+ * @param clear_flag    - log.1 will clear read flag on each clock tick
  * @param out           - recieved data
  * @param ready         - flag signifying whether new data are ready
  */
@@ -24,7 +24,6 @@ module receiver(
     /* Represents sum of three measurements at start bit. */
     reg[2:0]    start_bit_value;
     /* Handle previous value from clear_flag param. */
-    reg         prev_clear_flag;
     
     /**
      * Represents which bit is currently read:
@@ -90,10 +89,8 @@ module receiver(
      */
     always @(posedge clock)
     begin
-        prev_clear_flag <= clear_flag;
-    
-        /* Clear only at clear_flag rising edge. */
-        if (clear_flag && !prev_clear_flag)
+        /* Clear ready flag. */
+        if (clear_flag)
         begin
             ready <= 0;
         end

uart.py

@@ -2,27 +2,32 @@ import serial
 import serial.tools.list_ports as ports
 
 
-def sendAF(port):
+def send(port, num):
     ser = serial.Serial(port, 115200)
 
-    num = 0x69
     packet = bytearray([num])
 
     ser.write(packet)
     ser.close()
 
 
-def readBlock(port, n):
+def readBlock(port):
     ser = serial.Serial(port, 115200)
 
-    for _ in range(n):
-        num = ser.read()
+    num = ser.read()
+    
+    ser.close()
 
-        print(num.hex())
+    return num
 
-    ser.close()
 
 if __name__ == '__main__':
     print(list(map(lambda x: x.device, ports.comports())))
-    sendAF('COM3')
-    #readBlock('COM3', 5)
+
+    x = int(input('First number: '))
+    send('COM3', x)
+
+    y = int(input('Second number: '))
+    send('COM3', y)
+    
+    print('output: ', readBlock('COM3'))

uart.qsf

@@ -204,7 +204,5 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VERILOG_FILE clock_divider.v
 set_global_assignment -name VERILOG_FILE transmiter.v
-set_global_assignment -name VERILOG_FILE transmiter_example.v
-set_global_assignment -name VERILOG_FILE receiver_example.v
 set_global_assignment -name VERILOG_FILE receiver.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

uart.v

+/**
+ * Simple application which set up UART modules
+ * wait for two bytes and send back the bigger one.
+ */
 module uart(
     input           CLOCK_50,
     input   [3:0]   KEY,
@@ -5,19 +9,128 @@ module uart(
     inout   [1:0]   GPIO_0,
     output  [9:0]   LEDR
 );
+    
+    wire TX;
+    wire RX;
+
+    /* Assign UART pins. (RX = left, TX = right) */    
+    assign GPIO_0[0]    = TX;    
+    assign RX           = GPIO_0[1];
+    
+    /* Create UART clocks with max baudrate (115.2 kHz). */
+    wire uart_transmitter_clock;
+    wire uart_receiver_clock;
+    
+    clock_divider _uart_transmitter_clock(
+        .clock(CLOCK_50),
+        .out(uart_transmitter_clock)
+    );
+    
+    clock_divider _uart_receiver_clock(
+        .clock(CLOCK_50),
+        .out(uart_receiver_clock)
+    );
+    
+    defparam _uart_transmitter_clock.divider = 434;
+    defparam _uart_receiver_clock.divider = 62;
 
-    //transmiter_example example(
-    //    ._CLOCK_50(CLOCK_50),
-    //    ._KEY(KEY[0]),
-    //    ._SW(SW[7:0]),
-    //    ._GPIO_0(GPIO_0[0])
-    //);
-    
-    receiver_example example(
-        ._CLOCK_50(CLOCK_50),
-        ._KEY(KEY[0]),
-        ._GPIO_0(GPIO_0[1]),
-        ._LEDR(LEDR)
+    /* Predefine UART registers and wires. */
+    reg[7:0]    uart_transmit_data;
+    reg         uart_transmit_start;
+    wire        uart_transmit_ready;
+    
+    reg         uart_receiver_clear;
+    wire[7:0]   uart_receiver_data;
+    wire        uart_receiver_ready;
+    
+    /* Set UART modules. */
+    transmiter _trensmiter(
+        .clock(uart_transmitter_clock),
+        .start(uart_transmit_start),
+        .data(uart_transmit_data),
+        .out(TX),
+        .ready(uart_transmit_ready)
     );
+    
+    receiver _receiver(
+        .in(RX),
+        .clock(uart_receiver_clock),
+        .clear_flag(uart_receiver_clear),
+        .out(uart_receiver_data),
+        .ready(uart_receiver_ready)
+    );
+    
+    /* Define state machine. */
+    reg[2:0]    state;
+    localparam  state_wait_for_first    = 32'd0;
+    localparam  state_first_received    = 32'd1; 
+    localparam  state_wait_for_second   = 32'd2;
+    localparam  state_second_received   = 32'd3;
+    localparam  state_send_data         = 32'd4;
+    localparam  state_data_sent         = 32'd5;
+    
+    /* Helping registers. */
+    reg[7:0]    first_byte;
+    reg[7:0]    second_byte;
+    
+    /* Debug. */
+    reg[7:0]    LED;
+    
+    assign LEDR = LED;
+    
+    
+    /*remove*/
+    reg prev;
+    
+    /* Main loop */ 
+    always @(posedge uart_transmitter_clock)
+    begin
+        LED <= first_byte | second_byte;
+        
+        case (state)
+            state_wait_for_first:
+            begin
+                if (uart_receiver_ready == 1)
+                begin 
+                    state                   <= state_first_received;
+                    first_byte              <= uart_receiver_data;
+                    uart_receiver_clear     <= 1;
+                end
+            end
+            state_first_received:
+            begin
+                state                   <= state_wait_for_second;
+                uart_receiver_clear     <= 0;
+            end
+            state_wait_for_second:
+            begin
+                if (uart_receiver_ready == 1)
+                begin 
+                    state                   <= state_second_received;
+                    second_byte             <= uart_receiver_data;
+                    uart_receiver_clear     <= 1;
+                end
+            end
+            state_second_received:
+            begin
+                state                   <= state_send_data;
+                uart_receiver_clear     <= 0;
+            end
+            state_send_data:
+            begin
+                state               <= state_data_sent; 
+                uart_transmit_data  <= (first_byte > second_byte) ? first_byte : second_byte;
+                uart_transmit_start <= 1;
+            end
+            state_data_sent:
+            begin
+                if (uart_transmit_ready)
+                begin
+                    state               <= state_wait_for_first;
+                    uart_transmit_start <= 0;
+                end
+            end
+        endcase
+    end
 
 endmodule