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Commit 35061546 authored by Ján Labuda's avatar Ján Labuda
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feat: add docs

parent b70121ab
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receiver.v
View file @ 35061546
/**
* Loads data using UART protocol.
*
* @param in - UART link wire
* @param clock - clock with 7 times higher frequency then UART
* @param clear_flag - on rising edge, ready flag will be cleared
* @param out - recieved data
* @param ready - flag signifying whether new data are ready
*/
module receiver(
input wire in,
input wire clock, /* baudrate * 7 hertz */
output reg[7:0] out
input wire clock,
input wire clear_flag,
output reg[7:0] out,
output reg ready
);
reg[7:0] data;
/* Represents sum of three measurements at single bit. */
reg[2:0] current_bit_value;
/* Represents sum of three measurements at stop bit. */
reg[2:0] stop_bit_value;
/* Represents sum of three measurements at start bit. */
reg[2:0] start_bit_value;
reg[3:0] state_read; // 1 - 10 = reading given bit
reg[2:0] state_bit;
/* Handle previous value from clear_flag param. */
reg prev_clear_flag;
/**
* Represents which bit is currently read:
* 0 currently is not reading.
* 1 reading start bit.
* 2 - 9 reading data bit.
* 10 readint stop bit.
*/
reg[3:0] state_read;
localparam state_read_nop = 0;
localparam state_read_start_bit = 1;
localparam state_read_first_data_bit = 2;
localparam state_read_stop_bit = 10;
localparam state_read_last_bit = 10;
/**
* Each bit is computed from three measured values,
* made in separate time segments durning read:
* 0 - 1 nothing
* 2 reading first value
* 3 reading second value
* 4 reading third value
* 5 compute resulting value using weight
* 6 last segment
*/
reg[2:0] state_bit;
localparam state_bit_first_read = 2;
localparam state_bit_second_read = 3;
localparam state_bit_third_read = 4;
localparam state_bit_calculate = 5;
localparam state_bit_last_segment = 6;
/* Bit state machine */
/**
* State machine handling current reading state.
* First readed log.0 wil beggin reading of data.
*/
always @(posedge clock)
begin
if (in == 0 && state_read == state_read_nop) /* Begin receiving */
/* Start reading data on first log.0. */
if (in == 0 && state_read == state_read_nop)
begin
state_bit <= 1;
state_read <= 1;
end
else if (state_read == state_read_last_bit && state_bit == state_bit_last_segment) /* End reading */
/* End if read all data. */
else if (state_read == state_read_last_bit && state_bit == state_bit_last_segment)
begin
state_bit <= 0;
state_read <= 0;
end
else if (state_read != state_read_nop) /* Continue in receiving */
end
/* Keep reading. */
else if (state_read != state_read_nop)
begin
state_bit <= (state_bit == 6) ? 0 : state_bit + 1;
state_read <= (state_bit == 6) ? state_read + 1 : state_read;
......@@ -44,44 +84,64 @@ module receiver(
end
/* Reading data */
/**
* Read data according to given states. If read packet was not in the
* correct format,
*/
always @(posedge clock)
begin
prev_clear_flag <= clear_flag;
/* Clear only at clear_flag rising edge. */
if (clear_flag && !prev_clear_flag)
begin
ready <= 0;
end
/* Idle state. */
if (state_read == state_read_nop)
begin
data <= data;
if (start_bit_value < 2 && stop_bit_value > 1) /* Publish data if correct */
/* Check if start and stop bit weights ar correct. */
if (start_bit_value < 2 && stop_bit_value > 1)
begin
out <= data;
data <= 0;
out <= data;
data <= 0;
ready <= 1;
end
/* Clear previous data */
/* Clear previous data. */
start_bit_value <= 0;
stop_bit_value <= 0;
end
if (state_read == state_read_start_bit) /* Read start bit */
/* Read start bit. */
if (state_read == state_read_start_bit)
begin
/* Load weights. */
case (state_bit)
state_bit_first_read: start_bit_value <= start_bit_value + in;
state_bit_second_read: start_bit_value <= start_bit_value + in;
state_bit_third_read: start_bit_value <= start_bit_value + in;
endcase
end
/* Read stop bit. */
if (state_read == state_read_stop_bit) /* Read stop bit */
begin
/* Load weights. */
case (state_bit)
state_bit_first_read: stop_bit_value <= stop_bit_value + in;
state_bit_second_read: stop_bit_value <= stop_bit_value + in;
state_bit_third_read: stop_bit_value <= stop_bit_value + in;
endcase
end
/* Read data bits. */
if (1 < state_read && state_read < 10) /* Read data bits */
begin
case (state_bit)
/* Load weights. */
state_bit_first_read: current_bit_value <= current_bit_value + in;
state_bit_second_read: current_bit_value <= current_bit_value + in;
state_bit_third_read: current_bit_value <= current_bit_value + in;
/* Compute bit value using weights. */
state_bit_calculate:
begin
data <= current_bit_value > 1
......
transmiter.v
View file @ 35061546
/**
* Transmiter loads data from 'data' input at posedge from 'start'
* and start their transmission after 'start' is falled down.
* Current transmitted bit is sended through 'out'. When module
* is ready to load new data, 'ready' is held in log. 1.
* Sends data using UART protocol.
*
* @params clock - clock with same frequency as UART
* @params start - on negedge module will start transmiting if it is free,
* if pressed before module is ready, transmission will be paused
* @params data - data to transmit
* @params ready - holds log.0 when module is bussy
* @params out - output of the transmission
*/
module transmiter(
input wire clock,
......@@ -16,9 +20,14 @@ module transmiter(
parameter start_bit = 1'b0;
parameter stop_bit = 1'b1;
reg [9:0] _data;
reg [3:0] _to_transmit;
/**
* Current data with start and stop bits and
* numbers of bits to be transmitted.
*/
reg [9:0] packet;
reg [3:0] to_transmit;
/* Transmit data. */
always @(posedge clock, posedge start)
begin
if (start)
......@@ -28,19 +37,22 @@ module transmiter(
out <= 1;
ready <= 0;
_to_transmit <= 10;
_data <= (stop_bit << 9) | (data << 1) | start_bit;
/* Load data with bits to the buffer. */
to_transmit <= 10;
packet <= (stop_bit << 9) | (data << 1) | start_bit;
end
end
else if (_to_transmit > 0)
else if (to_transmit > 0)
begin
out <= _data[0];
out <= packet[0];
_to_transmit <= _to_transmit - 1;
_data <= _data >> 1;
/* Shift bits in buffer. */
to_transmit <= to_transmit - 1;
packet <= packet >> 1;
end
else
begin
/* Set ready state. */
out <= 1;
ready <= 1;
end
......
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