Commit b70121ab authored by Ján Labuda's avatar Ján Labuda
Browse files

feat: add receiver

parent b45434e3
module clock_divider(
input wire clock,
input wire reset,
input wire clock,
input wire reset,
output reg out
output reg out
);
parameter divider = 32'd50_000_000;
......
module receiver(
input wire in,
input wire clock, /* baudrate * 7 hertz */
output reg[7:0] out
);
reg[7:0] data;
reg[2:0] current_bit_value;
reg[2:0] stop_bit_value;
reg[2:0] start_bit_value;
reg[3:0] state_read; // 1 - 10 = reading given bit
reg[2:0] state_bit;
localparam state_read_nop = 0;
localparam state_read_start_bit = 1;
localparam state_read_first_data_bit = 2;
localparam state_read_stop_bit = 10;
localparam state_read_last_bit = 10;
localparam state_bit_first_read = 2;
localparam state_bit_second_read = 3;
localparam state_bit_third_read = 4;
localparam state_bit_calculate = 5;
localparam state_bit_last_segment = 6;
/* Bit state machine */
always @(posedge clock)
begin
if (in == 0 && state_read == state_read_nop) /* Begin receiving */
begin
state_bit <= 1;
state_read <= 1;
end
else if (state_read == state_read_last_bit && state_bit == state_bit_last_segment) /* End reading */
begin
state_bit <= 0;
state_read <= 0;
end
else if (state_read != state_read_nop) /* Continue in receiving */
begin
state_bit <= (state_bit == 6) ? 0 : state_bit + 1;
state_read <= (state_bit == 6) ? state_read + 1 : state_read;
end
end
/* Reading data */
always @(posedge clock)
begin
if (state_read == state_read_nop)
begin
data <= data;
if (start_bit_value < 2 && stop_bit_value > 1) /* Publish data if correct */
begin
out <= data;
data <= 0;
end
/* Clear previous data */
start_bit_value <= 0;
stop_bit_value <= 0;
end
if (state_read == state_read_start_bit) /* Read start bit */
begin
case (state_bit)
state_bit_first_read: start_bit_value <= start_bit_value + in;
state_bit_second_read: start_bit_value <= start_bit_value + in;
state_bit_third_read: start_bit_value <= start_bit_value + in;
endcase
end
if (state_read == state_read_stop_bit) /* Read stop bit */
begin
case (state_bit)
state_bit_first_read: stop_bit_value <= stop_bit_value + in;
state_bit_second_read: stop_bit_value <= stop_bit_value + in;
state_bit_third_read: stop_bit_value <= stop_bit_value + in;
endcase
end
if (1 < state_read && state_read < 10) /* Read data bits */
begin
case (state_bit)
state_bit_first_read: current_bit_value <= current_bit_value + in;
state_bit_second_read: current_bit_value <= current_bit_value + in;
state_bit_third_read: current_bit_value <= current_bit_value + in;
state_bit_calculate:
begin
data <= current_bit_value > 1
? (data | (1 << (state_read - state_read_first_data_bit)))
: data;
current_bit_value <= 0;
end
endcase
end
end
endmodule
module receiver_example(
input wire _CLOCK_50,
input wire _KEY,
inout wire _GPIO_0,
output reg [7:0] _LEDR
);
wire RX;
assign RX = _GPIO_0;
wire uart_clock;
wire[7:0] uart_data;
clock_divider divider(
.clock(_CLOCK_50),
.out(uart_clock)
);
defparam divider.divider = 62; /* 115.2 * 7 kHz */
//defparam divider.divider = 50_000_000;
receiver receiver(
.in(RX),
//.in(_KEY),
.clock(uart_clock),
.out(uart_data)
);
always @(posedge _CLOCK_50)
begin
_LEDR <= uart_data;
end
endmodule
......@@ -5,12 +5,12 @@
* is ready to load new data, 'ready' is held in log. 1.
*/
module transmiter(
input wire clock,
input wire start,
input wire[7:0] data,
input wire clock,
input wire start,
input wire[7:0] data,
output reg ready,
output reg out
output reg ready,
output reg out
);
parameter start_bit = 1'b0;
......
......@@ -5,7 +5,7 @@ import serial.tools.list_ports as ports
def sendAF(port):
ser = serial.Serial(port, 115200)
num = 0xAF
num = 0x69
packet = bytearray([num])
ser.write(packet)
......@@ -24,5 +24,5 @@ def readBlock(port, n):
if __name__ == '__main__':
print(list(map(lambda x: x.device, ports.comports())))
#sendAF('COM3')
readBlock('COM3', 5)
sendAF('COM3')
#readBlock('COM3', 5)
......@@ -205,4 +205,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE clock_divider.v
set_global_assignment -name VERILOG_FILE transmiter.v
set_global_assignment -name VERILOG_FILE transmiter_example.v
set_global_assignment -name VERILOG_FILE receiver_example.v
set_global_assignment -name VERILOG_FILE receiver.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
File deleted
......@@ -6,11 +6,18 @@ module uart(
output [9:0] LEDR
);
transmiter_example example(
//transmiter_example example(
// ._CLOCK_50(CLOCK_50),
// ._KEY(KEY[0]),
// ._SW(SW[7:0]),
// ._GPIO_0(GPIO_0[0])
//);
receiver_example example(
._CLOCK_50(CLOCK_50),
._KEY(KEY[0]),
._SW(SW[7:0]),
._GPIO_0(GPIO_0[0])
._GPIO_0(GPIO_0[1]),
._LEDR(LEDR)
);
endmodule
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