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Ján Labuda
FPGA - UART
Commits
07aa697c
Commit
07aa697c
authored
Dec 15, 2021
by
Ján Labuda
Browse files
feat: add frequency choose state machine
parent
30e31a95
Changes
6
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clock_divider.v
View file @
07aa697c
module
clock_divider
(
input
wire
clock
,
input
wire
reset
,
/**
* Clock divider with inbuilt prescaler.
*
* @param clock - clock input
* @param reset - reset current tick
* @param prescale_value - avaliable prescaler fur further division
* @param out - output of divided clocks
*/
module
clock_divider
(
input
wire
clock
,
input
wire
reset
,
input
wire
[
3
:
0
]
prescale_value
,
output
reg
out
output
reg
out
);
parameter
divider
=
32'd50_000_000
;
reg
[
31
:
0
]
counter
;
reg
[
31
:
0
]
counter
;
reg
[
3
:
0
]
current_prescale_value
;
always
@
(
posedge
clock
)
begin
if
(
reset
||
!
counter
)
counter
<=
divider
;
else
if
(
reset
)
begin
counter
<=
counter
-
1
;
end
else
if
(
current_prescale_value
>
1
)
begin
current_prescale_value
<=
current_prescale_value
-
1
;
end
else
begin
current_prescale_value
<=
prescale_value
;
out
<=
counter
==
0
;
if
(
!
counter
)
counter
<=
divider
;
else
counter
<=
counter
-
1
;
out
<=
counter
==
0
;
end
;
end
endmodule
display.v
View file @
07aa697c
/**
* Helping module to join seven segments of the display
* to single one.
*
* @param data - data to display
* @param digits - encoded data for display
*/
module
display
(
input
wire
[
23
:
0
]
data
,
...
...
prescaler_state_machine.v
View file @
07aa697c
/**
* Module helping for choosing desired baudrate used in UART.
*
* @param
* @param
* @param
* @param
* @param
* @param
clock - clock used for the output change
* @param
reset - reset state machine to first state (9600 bauds)
* @param
next - button input for picking next state
* @param
prescale_value - choosed prescaler value (using 115200 Hz clock)
* @param
prescale_display - choosed prescale baudrate for display purposes
*/
module
prescaler_state_machine
(
input
wire
clock
,
...
...
segment.v
View file @
07aa697c
/**
* Module to encode one hexa symbol to the display.
*
* @param data - data to encode
* @param segment_value - resulting value used for display
*/
module
segment
(
input
wire
[
3
:
0
]
data
,
input
wire
[
3
:
0
]
data
,
output
reg
[
6
:
0
]
segment_value
);
...
...
uart.qws
View file @
07aa697c
No preview for this file type
uart.v
View file @
07aa697c
/**
* Simple application which set up UART modules
* wait for two bytes and send back the bigger one.
* Application will let you first pick frequency using
* [KEY1] to pick next frequency and [KEY0] to reset
* current pick. Frequency is then choosed using [KEY2].
* After that application will read two bytes from UART
* pins and send the bigger one after one second delay.
*/
module
uart
(
input
CLOCK_50
,
...
...
@@ -9,14 +12,41 @@ module uart(
inout
wire
[
1
:
0
]
GPIO_0
,
output
wire
[
9
:
0
]
LEDR
,
output
wire
[
6
:
0
]
HEX0
,
output
wire
[
6
:
0
]
HEX1
,
output
wire
[
6
:
0
]
HEX2
,
output
wire
[
6
:
0
]
HEX3
,
output
wire
[
6
:
0
]
HEX4
,
output
wire
[
6
:
0
]
HEX5
output
wire
[
6
:
0
]
HEX0
,
output
wire
[
6
:
0
]
HEX1
,
output
wire
[
6
:
0
]
HEX2
,
output
wire
[
6
:
0
]
HEX3
,
output
wire
[
6
:
0
]
HEX4
,
output
wire
[
6
:
0
]
HEX5
);
/* Define prescaler selection state machine. */
wire
[
3
:
0
]
prescale_value_pick
;
wire
[
23
:
0
]
prescale_display_pick
;
prescaler_state_machine
prescale_module
(
.
clock
(
CLOCK_50
),
.
reset
(
!
KEY
[
0
]),
.
next
(
!
KEY
[
1
]),
.
prescale_value
(
prescale_value_pick
),
.
prescale_display
(
prescale_display_pick
)
);
/* Store value for prescaler. */
reg
[
23
:
0
]
baudrate
;
reg
[
3
:
0
]
prescale_value
;
reg
[
3
:
0
]
current_prescale
;
/**
* Display picked frequency depending on the value
* of an prescaler (default frequency is 115200).
*/
display
display
(
.
data
(
baudrate
),
.
digits
(
{
HEX5
,
HEX4
,
HEX3
,
HEX2
,
HEX1
,
HEX0
}
)
);
/* UART wires. */
wire
TX
;
wire
RX
;
...
...
@@ -28,18 +58,25 @@ module uart(
wire
uart_transmitter_clock
;
wire
uart_receiver_clock
;
/*
clock_divider _uart_transmitter_clock(
clock_divider
_u
art_transmitter_clock
(
.
clock
(
CLOCK_50
),
.
prescale_value
(
prescale_value
),
.
out
(
uart_transmitter_clock
)
);
clock_divider
_u
art_receiver_clock
(
.
clock
(
CLOCK_50
),
.
prescale_value
(
prescale_value
),
.
out
(
uart_receiver_clock
)
);
/**
* Desired values for default 115200 bauds.
* To test if prescaler work, set them to
* 217, 31 and use baudrate 57600.
*/
defparam
_u
art_transmitter_clock
.
divider
=
434
;
defparam _uart_receiver_clock.divider = 62;
*/
defparam
_u
art_receiver_clock
.
divider
=
62
;
/* Predefine UART registers and wires. */
reg
[
7
:
0
]
uart_transmit_data
;
...
...
@@ -51,7 +88,7 @@ module uart(
wire
uart_receiver_ready
;
/* Set UART modules. */
/*
transmiter _trensmiter(
transmiter
_
trensmiter
(
.
clock
(
uart_transmitter_clock
),
.
start
(
uart_transmit_start
),
.
data
(
uart_transmit_data
),
...
...
@@ -65,16 +102,18 @@ module uart(
.
clear_flag
(
uart_receiver_clear
),
.
out
(
uart_receiver_data
),
.
ready
(
uart_receiver_ready
)
);
*/
);
/* Define state machine. */
reg
[
2
:
0
]
state
;
localparam
state_wait_for_first
=
32'd0
;
localparam
state_first_received
=
32'd1
;
localparam
state_wait_for_second
=
32'd2
;
localparam
state_second_received
=
32'd3
;
localparam
state_send_data
=
32'd4
;
localparam
state_data_sent
=
32'd5
;
localparam
state_set_frequency
=
3'd0
;
localparam
state_frequency_pick
=
3'd1
;
localparam
state_wait_for_first
=
3'd2
;
localparam
state_first_received
=
3'd3
;
localparam
state_wait_for_second
=
3'd4
;
localparam
state_second_received
=
3'd5
;
localparam
state_send_data
=
3'd6
;
localparam
state_data_sent
=
3'd7
;
/* Helping registers. */
reg
[
7
:
0
]
first_byte
;
...
...
@@ -91,11 +130,21 @@ module uart(
localparam
second_delay
=
115200
;
/* Main loop */
/*
always @(posedge uart_transmitter_clock)
always
@
(
posedge
uart_transmitter_clock
)
begin
LED <= state;
LED
<=
1
<<
state
;
case
(
state
)
state_set_frequency:
begin
state
<=
(
!
KEY
[
2
])
?
state_frequency_pick
:
state_set_frequency
;
baudrate
<=
prescale_display_pick
;
prescale_value
<=
prescale_value_pick
;
end
state_frequency_pick:
begin
state
<=
(
KEY
[
2
])
?
state_wait_for_first
:
state_frequency_pick
;
end
state_wait_for_first:
begin
if
(
uart_receiver_ready
==
1
)
...
...
@@ -148,40 +197,6 @@ module uart(
end
end
endcase
end*/
wire
clk
;
clock_divider
simple_divider
(
.
clock
(
CLOCK_50
),
.
out
(
clk
)
);
defparam
simple_divider
.
divider
=
434
;
wire
[
3
:
0
]
prescale_value_pick
;
wire
[
23
:
0
]
prescale_display_pick
;
reg
[
23
:
0
]
baudrate
;
reg
[
3
:
0
]
prescale_value
;
display
display
(
.
data
(
baudrate
),
.
digits
(
{
HEX5
,
HEX4
,
HEX3
,
HEX2
,
HEX1
,
HEX0
}
)
);
prescaler_state_machine
prescale_module
(
.
clock
(
CLOCK_50
),
.
reset
(
!
KEY
[
0
]),
.
next
(
!
KEY
[
1
]),
.
prescale_value
(
prescale_value_pick
),
.
prescale_display
(
prescale_display
)
);
always
@
(
posedge
CLOCK_50
)
begin
LED
<=
prescale_value_pick
;
baudrate
<=
prescale_display_pick
;
end
endmodule
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