feat: add usb to uart example

clock_divider.v

-module clock_divider(
+    module clock_divider(
     input wire clock,
     input wire reset,
     

transmiter.v

+/**
+ * Transmiter loads data from 'data' input at posedge from 'start'
+ * and start their transmission after 'start' is falled down.
+ * Current transmitted bit is sended through 'out'. When module
+ * is ready to load new data, 'ready' is held in log. 1.
+ */
 module transmiter(
     input wire      clock,
     input wire      start,
     input wire[7:0] data,
     
-    output reg ready            ,//TODO REMOVE
+    output reg ready,
     output reg out
 );
     
-    parameter start_bit = 1;
-    parameter stop_bit  = 1;
+    parameter start_bit = 1'b0;
+    parameter stop_bit  = 1'b1;
 
     reg [9:0] _data;
     reg [3:0] _to_transmit;
@@ -19,23 +25,23 @@ module transmiter(
         begin
             if (ready)
             begin
-                out     <= 0;
+                out     <= 1;
                 ready   <= 0;
                 
                 _to_transmit    <= 10;
-                _data           <= (start_bit << 9) | (data << 1) | stop_bit; 
+                _data           <= (stop_bit << 9) | (data << 1) | start_bit; 
             end
         end
         else if (_to_transmit > 0)
         begin
-            out <= _data[9];
+            out <= _data[0];
             
             _to_transmit    <= _to_transmit - 1;
-            _data           <= _data << 1;
+            _data           <= _data >> 1;
         end
         else
         begin
-            out     <= 0;
+            out     <= 1;
             ready   <= 1;
         end
     end 

transmiter_example.v

+module transmiter_example(
+    input           _CLOCK_50,
+    input           _KEY,
+    input   [7:0]   _SW,
+    inout           _GPIO_0
+);
+
+    reg TX;
+    wire[9:0] SWITCH;
+        
+    assign SWITCH = _SW;
+    assign _GPIO_0 = TX;
+
+    reg[7:0]    uart_data;
+    reg         uart_start;
+    wire        uart_clock;
+    wire        uart_bit;    
+    
+    clock_divider divider(
+        .clock(_CLOCK_50),
+        .out(uart_clock)
+    );
+    
+    defparam divider.divider = 434; /* 115.2 kHz */
+
+    transmiter trensmit(
+        .clock(uart_clock),
+        .start(uart_start),
+        .data(uart_data),
+        .out(uart_bit)
+    );
+    
+    always @(posedge _CLOCK_50)
+    begin
+        uart_data   <= SWITCH[7:0];
+        uart_start  <= !_KEY;
+        
+        TX          <= uart_bit;
+    end
+
+endmodule

uart.qsf

@@ -204,4 +204,5 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VERILOG_FILE clock_divider.v
 set_global_assignment -name VERILOG_FILE transmiter.v
+set_global_assignment -name VERILOG_FILE transmiter_example.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

uart.v

@@ -2,39 +2,15 @@ module uart(
     input           CLOCK_50,
     input   [3:0]   KEY,
     input   [9:0]   SW,
+    inout   [1:0]   GPIO_0,
     output  [9:0]   LEDR
 );
 
-    reg[9:0] LED;
-    reg[7:0] my_data;
-    wire[9:0] SWITCH;
-    wire my_clock;
-    wire my_ready;
-    wire my_received;
-    
-    clock_divider div(
-        .clock(CLOCK_50),
-        .reset(!KEY[0]),
-        .out(my_clock)
+    transmiter_example example(
+        ._CLOCK_50(CLOCK_50),
+        ._KEY(KEY[0]),
+        ._SW(SW[7:0]),
+        ._GPIO_0(GPIO_0[0])
     );
-    
-    transmiter trensmit(
-        .clock(my_clock),
-        .start(!KEY[1]),
-        .data(my_data),
-        .ready(my_ready),
-        .out(my_received)
-    );
-    
-    defparam div.divider = 12_500_000;
-    
-    assign LEDR = LED;
-    assign SWITCH = SW;
-
-    always @(posedge CLOCK_50)
-    begin
-        my_data <= SWITCH[7:0];            
-        LED <= my_received;
-    end
 
 endmodule