Commit 21d0d9a3 authored by Ján Labuda's avatar Ján Labuda
Browse files

feat: init project

parent ff105d86
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 15:23:31 December 10, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "15:23:31 December 10, 2021"
# Revisions
PROJECT_REVISION = "uart"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 15:23:31 December 10, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# uart_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY uart
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:23:31 DECEMBER 10, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "DE1-SoC Board"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL Custom
set_global_assignment -name EDA_INPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_design_synthesis
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_timing_analysis
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_formal_verification
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "Stamp (Timing)"
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT STAMP -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_location_assignment PIN_AF14 -to CLOCK_50
set_location_assignment PIN_AE26 -to HEX0[0]
set_location_assignment PIN_AE27 -to HEX0[1]
set_location_assignment PIN_AE28 -to HEX0[2]
set_location_assignment PIN_AG27 -to HEX0[3]
set_location_assignment PIN_AF28 -to HEX0[4]
set_location_assignment PIN_AG28 -to HEX0[5]
set_location_assignment PIN_AH28 -to HEX0[6]
set_location_assignment PIN_AJ29 -to HEX1[0]
set_location_assignment PIN_AH29 -to HEX1[1]
set_location_assignment PIN_AH30 -to HEX1[2]
set_location_assignment PIN_AG30 -to HEX1[3]
set_location_assignment PIN_AF29 -to HEX1[4]
set_location_assignment PIN_AF30 -to HEX1[5]
set_location_assignment PIN_AD27 -to HEX1[6]
set_location_assignment PIN_AB23 -to HEX2[0]
set_location_assignment PIN_AE29 -to HEX2[1]
set_location_assignment PIN_AD29 -to HEX2[2]
set_location_assignment PIN_AC28 -to HEX2[3]
set_location_assignment PIN_AD30 -to HEX2[4]
set_location_assignment PIN_AC29 -to HEX2[5]
set_location_assignment PIN_AC30 -to HEX2[6]
set_location_assignment PIN_AD26 -to HEX3[0]
set_location_assignment PIN_AC27 -to HEX3[1]
set_location_assignment PIN_AD25 -to HEX3[2]
set_location_assignment PIN_AC25 -to HEX3[3]
set_location_assignment PIN_AB28 -to HEX3[4]
set_location_assignment PIN_AB25 -to HEX3[5]
set_location_assignment PIN_AB22 -to HEX3[6]
set_location_assignment PIN_AA24 -to HEX4[0]
set_location_assignment PIN_Y23 -to HEX4[1]
set_location_assignment PIN_Y24 -to HEX4[2]
set_location_assignment PIN_W22 -to HEX4[3]
set_location_assignment PIN_W24 -to HEX4[4]
set_location_assignment PIN_V23 -to HEX4[5]
set_location_assignment PIN_W25 -to HEX4[6]
set_location_assignment PIN_V25 -to HEX5[0]
set_location_assignment PIN_AA28 -to HEX5[1]
set_location_assignment PIN_Y27 -to HEX5[2]
set_location_assignment PIN_AB27 -to HEX5[3]
set_location_assignment PIN_AB26 -to HEX5[4]
set_location_assignment PIN_AA26 -to HEX5[5]
set_location_assignment PIN_AA25 -to HEX5[6]
set_location_assignment PIN_AA14 -to KEY[0]
set_location_assignment PIN_AA15 -to KEY[1]
set_location_assignment PIN_W15 -to KEY[2]
set_location_assignment PIN_Y16 -to KEY[3]
set_location_assignment PIN_V16 -to LEDR[0]
set_location_assignment PIN_W16 -to LEDR[1]
set_location_assignment PIN_V17 -to LEDR[2]
set_location_assignment PIN_V18 -to LEDR[3]
set_location_assignment PIN_W17 -to LEDR[4]
set_location_assignment PIN_W19 -to LEDR[5]
set_location_assignment PIN_Y19 -to LEDR[6]
set_location_assignment PIN_W20 -to LEDR[7]
set_location_assignment PIN_W21 -to LEDR[8]
set_location_assignment PIN_Y21 -to LEDR[9]
set_location_assignment PIN_AB12 -to SW[0]
set_location_assignment PIN_AC12 -to SW[1]
set_location_assignment PIN_AF9 -to SW[2]
set_location_assignment PIN_AF10 -to SW[3]
set_location_assignment PIN_AD11 -to SW[4]
set_location_assignment PIN_AD12 -to SW[5]
set_location_assignment PIN_AE11 -to SW[6]
set_location_assignment PIN_AC9 -to SW[7]
set_location_assignment PIN_AD10 -to SW[8]
set_location_assignment PIN_AE12 -to SW[9]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity week_05 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity week_05 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity week_05 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] -entity week_05
set_location_assignment PIN_AC18 -to GPIO_0[1]
set_location_assignment PIN_Y17 -to GPIO_0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] -entity week_05
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0 -entity week_05
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity week_05 -section_id Top
set_global_assignment -name VERILOG_FILE uart.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
module uart(
input CLOCK_50,
output [9:0] LEDR,
input [9:0] SW
);
reg [9:0] LED;
wire [9:0] SWITCH;
assign LEDR = LED;
assign SWITCH = SW;
always @(posedge CLOCK_50)
begin
LED <= SWITCH;
end
endmodule
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