Commit d4a918e5 authored by Jan Koniarik's avatar Jan Koniarik
Browse files

added another pcbs

parent 6d241d5b
......@@ -25,3 +25,4 @@ fp-info-cache
*.xml
*.csv
pcb/*/out/
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include <../tile.scad>
projection()
tile_raw_plate(T24, 2, 4, 2);
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include <../tile.scad>
projection()
tile_raw_plate(T24, 3, 4, 2);
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update=Sat Jan 30 20:09:23 2021
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=1
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Device:Battery_Cell BT1
U 1 1 6015ACDE
P 5100 3950
F 0 "BT1" H 5218 4046 50 0000 L CNN
F 1 "Battery_Cell" H 5218 3955 50 0000 L CNN
F 2 "tile:18650_holder" V 5100 4010 50 0001 C CNN
F 3 "~" V 5100 4010 50 0001 C CNN
1 5100 3950
1 0 0 -1
$EndComp
Wire Wire Line
5100 4050 4900 4050
$Comp
L power:VCC #PWR0101
U 1 1 6015C33D
P 4900 3750
F 0 "#PWR0101" H 4900 3600 50 0001 C CNN
F 1 "VCC" H 4917 3923 50 0000 C CNN
F 2 "" H 4900 3750 50 0001 C CNN
F 3 "" H 4900 3750 50 0001 C CNN
1 4900 3750
1 0 0 -1
$EndComp
Connection ~ 4900 3750
Wire Wire Line
4900 3750 5100 3750
$Comp
L power:GND #PWR0102
U 1 1 6015C878
P 4900 4050
F 0 "#PWR0102" H 4900 3800 50 0001 C CNN
F 1 "GND" H 4905 3877 50 0000 C CNN
F 2 "" H 4900 4050 50 0001 C CNN
F 3 "" H 4900 4050 50 0001 C CNN
1 4900 4050
1 0 0 -1
$EndComp
Connection ~ 4900 4050
$Comp
L Connector:Conn_01x01_Male J1
U 1 1 611E2D1A
P 4650 3550
F 0 "J1" V 4712 3594 50 0000 L CNN
F 1 "Conn_01x01_Male" V 4803 3594 50 0000 L CNN
F 2 "MountingHole:MountingHole_3.5mm_Pad_Via" H 4650 3550 50 0001 C CNN
F 3 "~" H 4650 3550 50 0001 C CNN
1 4650 3550
0 1 1 0
$EndComp
$Comp
L Connector:Conn_01x01_Male J2
U 1 1 611E3324
P 4650 4250
F 0 "J2" V 4804 4162 50 0000 R CNN
F 1 "Conn_01x01_Male" V 4713 4162 50 0000 R CNN
F 2 "MountingHole:MountingHole_3.5mm_Pad_Via" H 4650 4250 50 0001 C CNN
F 3 "~" H 4650 4250 50 0001 C CNN
1 4650 4250
0 -1 -1 0
$EndComp
Wire Wire Line
4650 3750 4900 3750
Wire Wire Line
4650 4050 4900 4050
$Comp
L Device:Battery_Cell BT2
U 1 1 611E60DF
P 4050 3950
F 0 "BT2" H 4168 4046 50 0000 L CNN
F 1 "Battery_Cell" H 4168 3955 50 0000 L CNN
F 2 "tile:18650_holder" V 4050 4010 50 0001 C CNN
F 3 "~" V 4050 4010 50 0001 C CNN
1 4050 3950
1 0 0 -1
$EndComp
Wire Wire Line
4050 4050 3850 4050
$Comp
L power:VCC #PWR0103
U 1 1 611E60E6
P 3850 3750
F 0 "#PWR0103" H 3850 3600 50 0001 C CNN
F 1 "VCC" H 3867 3923 50 0000 C CNN
F 2 "" H 3850 3750 50 0001 C CNN
F 3 "" H 3850 3750 50 0001 C CNN
1 3850 3750
1 0 0 -1
$EndComp
Connection ~ 3850 3750
Wire Wire Line
3850 3750 4050 3750
$Comp
L power:GND #PWR0104
U 1 1 611E60EE
P 3850 4050
F 0 "#PWR0104" H 3850 3800 50 0001 C CNN
F 1 "GND" H 3855 3877 50 0000 C CNN
F 2 "" H 3850 4050 50 0001 C CNN
F 3 "" H 3850 4050 50 0001 C CNN
1 3850 4050
1 0 0 -1
$EndComp
Connection ~ 3850 4050
$Comp
L Connector:Conn_01x01_Male J3
U 1 1 611E60F5
P 3600 3550
F 0 "J3" V 3662 3594 50 0000 L CNN
F 1 "Conn_01x01_Male" V 3753 3594 50 0000 L CNN
F 2 "MountingHole:MountingHole_3.5mm_Pad_Via" H 3600 3550 50 0001 C CNN
F 3 "~" H 3600 3550 50 0001 C CNN
1 3600 3550
0 1 1 0
$EndComp
$Comp
L Connector:Conn_01x01_Male J4
U 1 1 611E60FB
P 3600 4250
F 0 "J4" V 3754 4162 50 0000 R CNN
F 1 "Conn_01x01_Male" V 3663 4162 50 0000 R CNN
F 2 "MountingHole:MountingHole_3.5mm_Pad_Via" H 3600 4250 50 0001 C CNN
F 3 "~" H 3600 4250 50 0001 C CNN
1 3600 4250
0 -1 -1 0
$EndComp
Wire Wire Line
3600 3750 3850 3750
Wire Wire Line
3600 4050 3850 4050
$EndSCHEMATC
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
update=Mon Dec 7 20:54:38 2020
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=1
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=1
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=1
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled